2008

• 12/01/2008Aldec® Delivers New Dual-FPGA Prototyping Solution for Actel® RTAX4000S Space-Flight FPGA Designs
• 11/17/2008Aldec Releases Unified 64-bit Multi-Threaded HDL Design Environment
• 11/10/2008Aldec Announces OVM World Partnership and Future Support for OVM 2.0
• 09/29/2008Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1
• 09/22/2008Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System
• 07/28/2008Aldec® Announces HES 2008.07 with SCE-MI 2.0 Co-Emulation Debugging and Dynamic Debugging for ASIC Design Emulation
• 06/23/2008Aldec Delivers Clock Domain Crossing (CDC) Solution
• 06/09/2008Aldec Enhances Entire EDA Suite with Key Verification Methodologies
• 06/03/2008Aldec Releases Riviera-PRO™ 2008.06 HDL Simulator. Including New Assertions Waveform Viewer and Seamless debugging of SystemC/C++ and HDL
• 04/28/2008Aldec Joins Altera DO-254 Global Partner Network Providing In-Hardware Verification of Altera’s FPGA Devices
• 04/23/2008Aldec® Delivers ASIC Design Emulation
• 04/21/2008Lattice and Aldec Announce New Alliance For FPGA Design And Verification
• 03/03/2008Aldec Launches Powerful Verilog Design Rule Checker
• 02/25/2008Aldec Releases Riviera-PRO™ 2008.02 with VHDL 2007, SystemC™ 2.2 and SystemVerilog (DPI)

2007

• 12/20/2007Aldec releases Active-HDL 7.3 and Introduces Multi-threaded HDL Compilation
• 10/31/2007Zuken and Aldec Deliver New Design Solution: CADSTAR FPGA
• 10/11/2007Aldec releases Riviera-PRO Targeting ASIC/FPGA Verification Market
• 06/11/2007Aldec releases STARC based Linting Tool
• 05/23/2007Zuken and Aldec Partner to Offer Complete FPGA Design and Verification Flow
• 05/14/2007Aldec Delivers Prototyping Solution for Actel RTAX-S Space FPGA Designs
• 04/09/2007Aldec supports The MathWorks Simulink® Fixed Point
• 04/05/2007Aldec Opens Japan Office
• 03/19/2007Aldec Announces Support for Altera's Low-Cost Cyclone III FPGAs
• 03/12/2007Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design
• 03/07/2007Aldec offers no-cost Active-HDL Student Edition. Mixed VHDL/Verilog and SystemC simulation support with direct Matlab/Simulink™
• 03/05/2007Aldec releases 64-bit mixed HDL Simulator
• 03/05/2007Riviera-Pro™ HDL simulation environment to support POSDATA WiMAX product development
• 02/21/2007Gaisler Research and Aldec partner to increase IP core availability and portability
• 01/26/2007Aldec and nSys partner to Deliver No Cost Verification IP for Evaluation
• 01/08/2007Lattice And Aldec Sign Mixed-Language Simulator Agreement

2006

• 12/11/2006Aldec releases Active-HDL version 7.2 featuring new performance gains and simulation technology