Read what users have to say about Active-HDL vs. Mentor ModelSIM in John Cooley’s independent report published at: Aldec crushes Mentor Article
"Thanks for the incredible seminar on assertions. I would like to thank you for arranging such a wonderful seminar with no marketing stuff in that. Overall I rate it 'Best' or 'Exceeded my Expectations' range."
Intel – Engineering Manager
"[Riviera’s] MatLab co-sim helped me catch an error in the Xilinx DSP48e mathematical operations. The error would have propagated the design and not been seen until in lab testing. In the past, this kind of error would have cost 2-4 weeks to isolate and correct. In addition, the direct MatLab link allows for a 30 second advanced simulation with full sim/stim (simulation and stimulation) capability of our top-level design that would have taken 5-6 hours in the past due to using text files for data transfers."
Lockheed Martin – Hardware Design Engineer
Active-HDL is the primary VHDL simulation environment used by students and faculty in the University of Florida (UF) site of the NSF Center for High-Performance Reconfigurable Computing (CHREC). The user interface of Active-HDL is very intuitive without the need for frequent reference of formal documentation. Our staff especially likes the feature that allows hotkeys to be assigned to signals. This feature works particularly well when discovering a problem during a long simulation that is not tested by a testbench. Instead of having to rewrite the testbench and rerun the simulation, we can quickly change a signal value to see the results. For some examples, this feature also eases testbench creation by giving manual control over specific signals. We have also found that some other simulators can have difficulties simulating moderate- to large-sized designs, complaining about the size of the simulation and incurring lengthy simulation times. The simulation speed of Active-HDL is impressive, even for large designs.
Dr. Alan D. George, University of Florida - CHREC
I use Active-HDL to teach Hardware Description Languages (CPE410 and EE610) in our University. Active-HDL is an Electronic Design Automation tool which is tailored to the needs of all designers using Programmable Logic Devices. I found Active HDL to be the best tool to teach VHDL. It is very user friendly, easy to use and versatile. My students find the on-line-documentation to be very useful. The language assistant and the wizards help in writing the code very quickly. I am appreciative of the customer support that is prompt and accurate. My graduate students who are designing an image processor find this tool more efficient than other tools for simulation and debugging. I would recommend Active-HDL to both students and designers.
Dr. Henry Selvaraj Professor and Chair Department of Electrical and Computer Engineering University of Nevada Las Vegas
"The simulation performance and user interface of Aldec's Active-HDL are simply superb. Every feature I needed was thoughtfully and elegantly in place. Thanks to Aldec's support team, learning how to simulate a new and rather complex design took nearly no time at all. It is quite clear that Aldec's engineers have left no stone unturned in their quest for excellence."
Jacob Yalcin Senior Systems Engineer Equinox Corporation
"Infra-Com's highly sophisticated wireless communication digital ASICs project had a very tight schedule - One of the main benefits of engaging with Aldec for the design entry and simulation of our ASIC chipset was to reduce the time to market and risks. For Infra-Com, two generations of successful products make Aldec a proven solution for the ASIC chipsets."
Uri Kanonich, Infra-Com's COO
"Aldec's simulator is a tremendous value for money. For the price, nothing near that good is available on the market. Aldec’s Active-HDL environment satisfies all our requirements for source code creation and debugging. It has a source code debugger, a waveform viewer, data flow diagrams generated on the fly. A memory viewer is also available, an important touch for a company like ours that develops processor cores. While we use simulators from other parties for the sake of script compliance testing, we have relied on Aldec's simulator as the key tool in our development process for several years."
Wojciech Sakowski CSO, Evatronix A silicon Intellectual Property (IP) provider
"I want to thank you for conducting Active-HDL training at Transcore. That is the kind of "after-the-sale" support most companies would be envious of!! Aldec remains a cut above the rest."
Lawrence Gorton Transcore Amtech Technology Center
"I use Active-HDL in my day to day operations; I find Aldec easy to use and the simulator performance is very competitive. Active-HDL is packaged with a complete design entry tool, and includes many integrated extras including automatic type-ahead of key names, block diagram and state machine editors, source control, IP macros, hooks to integrate implementation tools, code profiling and toggle coverage monitors. The ability to co-simulate with Matlabs is a huge time-saver when developing DSP designs. The integrated package makes the design process easier. The documentation that comes with the Aldec suite is without compare. It includes a complete detailed guide to the LRM, with many examples, and a tutorial that rivals the instruction given in professional courses on using Verilog and VHDL. For those just learning either of these languages, the tutorials alone are worth the price of the entire tool suite. Customer support from Aldec is also exemplary. In the rare occasions when I have experienced trouble with the tools, the technical support staff has always provided patches within a few days. If only the other EDA vendors were so conscientious. I highly recommend Active-HDL for anyone involved in FPGA design".
Ray Andraka, P.E. President, Andraka Consulting Group, Inc. A design firm specializing in high performance DSP designs using FPGAs, since 1994.
"Active-HDL is very user friendly and anyone can use the tool without much difficulty. Simulator performance is very fast and waveform portability using cut/paste is a very useful feature for documentation purposes. The block diagram entry is again a great feature for implementing top down design approach. Our groups overall productivity has increased substantially because of Active-HDL."
Venkatesan Sivaprakasam, Deputy Engineer, SED, Electronics Corporation of India Limited, Hyderabad, India
I was able to attend and thanks for the follow up. I'd like to also add to the positive feedback - it was very technical and very informative - perfect for us engineers. Kudos to you.
Comit Systems, Inc
"Comtech EF Data engineering has used and compared many other FPGA design entry and simulation tools. Active-HDL far surpass the competition in tool features and user-friendly interfaces; with a much lower price-tag."
Dennis Bennett, Comtech EF Data
"The Computer Science Department at Rowan University consists of thirteen highly qualified faculty members and two professional staff members. The department offers a Bachelor and Master of Science degree in Computer Science as well as a minor in Computer Science. Computer science students master current technology and develop the versatility needed to adapt in this fast evolving field. Recent graduates have found exciting careers in industry, government and education. The program also prepares students for graduate study in Computer Science and related fields. Specializations are available in the areas of software engineering, networking and operating systems, information technology, programming languages and compilers, and artificial intelligence. The Computer Science Department moved to Active-HDL as part of an initiative to introduce and teach Hardware Description Languages (VHDL) into the computer science curriculum for computer architecture and computer hardware that will benefit from Active HDL design. The curriculum includes Computer Organization, Principles of Digital Computers, Digital Computer Design Lab, Embedded System Design, and Advanced Computer Architecture.
We as Computer Science professionals and educators are always looking for effective means to facilitate learning and provide the “state of the art” experiences for our student. Your product provides just such an environment for our undergraduate hardware centered classes. We and our students have found Active-HDL to be a very versatile and an easy to use environment for developing digital components and systems. Further, our students find the ability to manage and test complex designs very helpful in removing the burden of learning a development environment from the design process. We believe that our students must be versed in both the hardware and software aspects of our profession to be relevant to a changing job market. Active-HDL and the integration of VHDL into our computer architecture course sequence provides the opportunity to our students to develop a deeper understanding of digital design and computer hardware. The built in documentation and wizards also eases the burden of learning the tool and the support that Aldec provides for this product is outstanding. I would recommend Active-HDL to any faculty, students or university looking to move forward with a design and simulation tool that allows more time to be devoted to learning computer hardware and digital design."
Dr. Nancy Tinkham, Professor and Chair, Computer Science Department, Rowan University
"The CBE SystemVerilog design and verification online courses were well organized, cost-effective, thorough and a very effective way to learn SystemVerilog. The Riviera-PRO license and numerous labs associated with each course reflected the course designer's personal expertise and enabled a valuable "learn by doing" experience."
Daniel L. Dauer, President/CEO, Dauer Consulting, Inc. ASIC/VLSI Design and Verification Engineering Services