Download White Papers, Technical Briefs and Articles addressing today’s leading technologies and Design Verification topics.
Aldec has developed a no cost Student Edition based on the popular Active-HDL design and simulation environment. This version represents a great opportunity for students to use a VHDL, Verilog and SystemC simulator.
This SystemC Primer is a Hands-On SystemC introduction. Your download will consist of both a presentation and 2 hands-on labs. Labs will consist of both a simple stand-Alone SystemC implementation and a VHDL interface example.
Evita-VHDL is an interactive VHDL primer that provides a comprehensive overview of the VHDL language, complete reference guide, over 150 examples and a series of questions and answers at the end of each chapter.
Evita-Verilog is an interactive Verilog primer that provides a comprehensive overview of the Verilog language, complete reference guide, over 130 examples and a series of questions and answers at the end of each chapter.
A series of no-cost webinars to help engineers understand emerging verification trends and technologies.