Events Schedule

Webinars

 LocationDate 
Design Rule Checking Tools: a Key to Avoiding ASIC Re-spins. On-Line December 17 Register
Europe - Design Rule Checking Tools: a Key to Avoiding ASIC Re-spins. On-Line December 17 Register
Actel & Aldec: Innovative Reprogrammable Prototyping for Actel RTAX Space-Flight FPGA Designs On-Line January 15 Register
Europe Actel & Aldec: Innovative Reprogrammable Prototyping for Actel RTAX Space-Flight FPGA Designs On-Line January 15 Register

Seminars

 LocationDate 
FPGA Design and Verification with Active-HDL Workshop Taipei, Taiwan December 05 Register
FPGA Design and Verification with Active-HDL Workshop Tainan, Taiwan December 12 Register
SystemVerilog Assertions Language and Methodology Overview Seminar Sunnyvale, CA December 16 Register

Trade Shows

 LocationDate 
FPGA Summit San Jose, CA December 10 - December 11 Register