Aldec - Products

FPGA and ASIC Verification Products

	Design Creation	Verification	Specialty Solutions
FPGA Verification
Active-HDL 8.1	Schematic / Block Diagram Editor HDL Text Editor State Machine Editor FPGA Project Management IP Core Generator Code to Graphics Testbench Generation Documentation (HTML/PDF)	VHDL Simulation Verilog Simulation SystemC SystemVerilog Code Coverage	MATLAB/Simulink Co-Simulation Verification IP HDL Regression Manager	Download Configurations Brochure (.pdf) Read More
ASIC/FPGA Verification
Riviera-PRO 2008.10	HDL Text Editor	VHDL Simulation Verilog Simulation SystemC SystemVerilog Assertions (PSL, SVA and OVA) Code Coverage Design Rule Checker (LINT)	MATLAB/Simulink Co-Simulation Verification IP HDL Regression Manager	Download Configurations Brochure (.pdf) Read More
ALINT 2008.06		Design Rule Checker (LINT)		Download Configurations Brochure (.pdf) Read More
In-Hardware Verification
HES 2008.07		Acceleration/Emulation	In-Hardware Simulation NIOS II Co-Verification ARM Co-Verification	Request Contact Configurations Brochure (.pdf) Read More
Specialty Solutions
Actel RTAX-S/SL Prototyping			Actel RTAX Prototyping EDIF Netlist Conversion	Download Brochure (.pdf) Read More
DO-254/CTS			In-Hardware Simulation DO-254 Compliance	Download Brochure (.pdf) Read More
IP Products
IP Products	IP Core Generator		Verification IP	Read More