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News & Events

Newsroom

FEB 20 2012 - Aldec to Address Biggest Safety and Mission-Critical Verification Challenges in Electronic Warfare at EWCI in India JAN 23 2012 - Aldec adds Documentation for Safety-Critical Designs in ALINT™ 2012.01 JAN 19 2012 - Q1-2012 - Aldec™ Design and Verification Newsletter JAN 13 2012 - Verification Engineers are Invited to Take a Brief Survey and Receive a Chance to win an Ipad2! JAN 09 2012 - Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™

Events

FEB 27 2012 - Design & Verification Conference (DVCon 2012) (Trade Shows) MAR 08 2012 - Bridging Analog and Digital Verification (US) (Webinars) MAR 08 2012 - Bridging Analog and Digital Verification (Europe) (Webinars) MAR 12 2012 - Design, Automation and Test in Europe (DATE ‘12) (Trade Shows) APR 16 2012 - 28th National Space Symposium (Trade Shows)

Recorded Webinars

Closed Loop Verification of Large Designs SystemVerilog: Who? What? When? Where? OVM and UVM - Building a SystemVerilog Testbench in Riviera-PRO Introducing Transactions in Design Verification Decrypting Encryption in HDL Design and Verification

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