Functional Verification
Riviera-PRO™ verification platform delivers advanced design entry, simulation, debugging, and verification tools based on cutting edge technology. Riviera-PRO integrates an extensive set of tools and features that delivers efficient FPGA and ASIC design and verification.
Top Features
- Advanced Verification Platform (UVM/OVM, VMM)
- Different Levels of Abstraction (ESL/TLM, RTL, Gate-Level)
- High-Performance Simulator for Mixed Language Designs
- IEEE VHDL, Verilog®, SystemVerilog, SystemC/C/C++
- Transaction-Level Debugging Environment
- Assertion-Based Verification (SVA, PSL and OVA)
- Code and Functional Coverage
- DSP Co-Simulation with MATLAB® and Simulink®
- Linux and Windows® 7/2008/Vista/XP/2003 32/64 Bit Support
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HDL Editor
Assertions & Cover
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Post Simulation Debug
Code Coverage
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