Project Management/Integration

FPGA Project Management

A typical FPGA design flow includes the design entry phase, synthesis, and implementation (fitting and Place & Route processing), each stage typically followed by simulation. Managing the project throughout the design flow along with the design data is becoming very important. The Design Flow Manager is the tool that is designed to automate these processes. It interfaces with the third party tools and provides FPGA designers a unique platform that can be used throughout the FPGA design flow.

Benefits of using FPGA Project Management: It encloses the entire FPGA design flow from design entry to place and route which means that you don’t have to learn different vendor tools during different phase of FPGA design It interfaces with 90+ vendor tools which allows you to configure your flow in many different ways It collaborates with the version/revision control system to provide data and version management for your project Built-in Server Farm allows designers to manage the queue for their simulation, synthesis, and implementation tasks

Testbench Generation

The Testbench Generation tool is designed for automatic generation of testbench files based on the user-defined specification. It can generate the empty shell of the testbench (without stimulus) or it can generate the fully functional testbench with stimulus. Test vector file is needed to generate the testbench with stimulus. A testbench generates stimulus for the UUT entity on the basis of test vectors defined in this file. Also a testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run.

Benefits of using Testbench Generation: Powerful testbench generation tool speeds up functional verification Generated testbenches are completely editable for further modification Automatic generation of testbenches for state machines allows you to create a testbench that fully tests the state machine The SystemC Verification Library (SCV) delivered with ALDEC tools allows creating constrained and randomized stimulus. SCV combined with the transactor methodology offers the designer a powerful tool to create advanced testbench that automatically generated stimulus as well MATLAB/Simulink interface can be used to employ advanced testbenches with complex mathematical formulas used to stimulate unit under test(UUT)